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High Performance, 12-Bit, 12-Channel Decimating, LCD DecDriver(R) AD8387
FEATURES
High accuracy, high-resolution voltage outputs 1 mV channel matching 12-bit input resolution Laser-trimmed outputs Fast settling, high voltage drive 35 ns settling time to 0.25% into 150 pF load Slew rate 420 V/s Outputs to within 1.3 V of supply rails High update rates Fast, 110 MHz clock Programmable video reference (brightness) and full-scale (contrast) output levels Flexible logic INV bit reverses polarity of video signal R/L reverses loading order of data ISW selects frame/row or column/dot inversion DSW selects single or dual data bus mode Output short-circuit protection 3.3 V logic, 11 V to 18 V analog supplies Available in 80-lead, 12 mm x 12 mm, TQFP E-pad
DBA(0:11) 12 12
FUNCTIONAL BLOCK DIAGRAM
12 12 TWO-STAGE 12 LATCH TWO-STAGE 12 LATCH DAC VID0
DBB(0:11)
DAC
VID1
BYP
BIAS THERMAL SWITCH G-MODE SWITCH
TSW
12 TWO-STAGE 12 LATCH 12 TWO-STAGE 12 LATCH
DAC
VID10
GSW DSW CLK XFR R/L
DAC
VID11
SEQUENCE CONTROL SCALING CONTROL
05653-001
AD8387
INV ISW VRH VRL
Figure 1.
APPLICATIONS
LCD microdisplay driver
GENERAL DESCRIPTION
The AD8387 DecDriver provides dual, fast latched, 12-bit decimating input, which drives 12 high voltage outputs. Twelvebit input words are loaded into 12 separate high speed, bipolar DACs sequentially. Flexible digital input format allows more than one AD8387 to be used in parallel for higher resolution displays. The output signal can be adjusted for dc reference, signal inversion, and contrast for maximum flexibility. The AD8387 is fabricated on ADI's fast bipolar, 26 V XFCB process, providing fast input logic, bipolar DACs with trimmed accuracy and fast settling, high voltage, precision drive amplifiers on the same chip. The AD8387 dissipates 1.34 W nominal static power. The AD8387 is offered in an 80-lead TQFP E-pad package and operates over the commercial temperature range of 0C to +85C.
5
VDE CHANNEL MATCHING (mV)
4
3 CODE 0 2
NORMAL PROJECTOR OPERATING TEMPERATURE RANGE
CODE 2048
1
CODE 4095
05653-015
0 0 10 20 30 40 50 60 70 80 INTERNAL AMBIENT TEMPERATURE (C)
Figure 2. Channel Matching vs. Temperature
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
AD8387 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Exposed Paddle............................................................................. 5 Overload Protection..................................................................... 5 Maximum Power Dissipation ..................................................... 5 Operating Temperature Range ................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 8 Timing Diagrams.............................................................................. 9 Single Data Bus Configuration, DSW = LOW ......................... 9 Dual Data Bus Configuration, DSW = HIGH........................ 10 Functional Description .................................................................. 12 Reference and Control Input Description............................... 12 Theory of Operation ...................................................................... 13 Transfer Function and Analog Output Voltage...................... 13 Accuracy ...................................................................................... 13 Applications..................................................................................... 14 Optimized Reliability with the Thermal Switch .................... 14 Initial Power-Up After Assembly or Repair............................ 14 Power-Up During Normal Operation ..................................... 14 Power Supply Sequencing ......................................................... 14 Power-On Sequence................................................................... 14 Power-Off Sequence................................................................... 14 Grounded Output Mode During Power-Off .......................... 14 PCB Design for Optimized Thermal Performance ............... 14 Thermal Pad Design .................................................................. 15 Thermal via Structure Design .................................................. 15 AD8387 PCB Design Recommendations ............................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16
REVISION HISTORY
10/05--Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD8387 SPECIFICATIONS
TA = 25C, AVCC = 15.5 V, DVCC = 3.3 V, VRH = 9.5 V, VRL = 7 V, TA MIN = 0C, TA MAX = 75C still air, unless otherwise noted. Table 1.
Parameter VIDEO DC PERFORMANCE 1 VDE--Differential Error Voltage Conditions TA MIN to TA MAX ,VFS = 5 V @ DAC code 0 @ DAC code 1024 @ DAC code 2048 @ DAC code 3072 @ DAC code 4095 DAC code range 0 to 4095 @ DAC code 0 @ DAC code 1024 @ DAC code 2048 @ DAC code 3072 @ DAC code 4095 DAC code range 0 to 4095 @ DAC code 0 @ DAC code 1024 @ DAC code 2048 @ DAC code 3072 @ DAC code 4095 DAC code range 0 to 4095 @ DAC code 0 @ DAC code 1024 @ DAC code 2048 @ DAC code 3072 @ DAC code 4095 DAC code range 0 to 4095 -1 TA MIN to TA MAX VIDx = 5 V step, CL = 150 pF 20% to 80% Min Typ Max Unit
-5.5 -4.4 -3.6 -2.8 -2.1 -6.0 -2.5 -2.5 -2.5 -2.5 -2.5 -3.5
-0.8 -0.5 -0.3 -0.3 +0.2
+5.0 +3.6 +3.3 +2.8 +2.1 +6.0 +2.5 +2.5 +2.5 +2.5 +2.5 +3.5 4.8 4.3 4.0 3.8 2.8 5.5
mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV mV LSB
VCME--Common-Mode Error Voltage
-0.3 -0.3 -0.3 -0.3 -0.3
VDE--VDE Channel Matching
1.9 1.8 1.6 1.4 1.0
V--Channel Matching
2.7 2.7 2.5 2.5 2.0 7.5 -0.2 35 22 420 15 69 50 0.4 70 34 700 25 150 40 50 28
DNL 2 VIDEO OUTPUT DYNAMIC PERFORMANCE Data Switching Settling Time to 0.25% Data Switching Settling Time to 1% Data Switching Slew Rate CLK and Data Feedthrough 3 All-Hostile Crosstalk 4 Amplitude Glitch Duration DAC Transition Glitch Energy Invert Switching Settling Time to 0.25% Invert Switching Settling Time to 1% Invert Switching Slew Rate Invert Switching Overshoot
ns ns V/s mV p-p mV p-p ns nV-s ns ns V/s mV
DAC Code 2047 to 2048 VIDx = 10 V step, CL = 150 pF 20% to 80%
Rev. 0 | Page 3 of 16
AD8387
Parameter VIDEO OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage--Grounded Mode Data Switching Delay: t7 5 Data Switching Delay Skew: t75 INV Switching Delay: t8 6 INV Switching Delay Skew: t86 Output Current Output Resistance REFERENCE INPUTS VRL Range VRH Range VRH to VRL Range1 VRH Input Resistance VRL Input Current VRH Input Current RESOLUTION DIGITAL INPUT CHARACTERISTICS CLK Frequency Data Setup Time: t1 XFR Setup Time: t3 Data Hold Time: t2 XFR Hold Time: t4 CLK High Time: t5 CLK Low Time: t6 CLK High Time: t7 CLK Low Time: t8 CIN IIH IIH TSW IIH XFR IIL IIL TSW IIL XFR VIH VIL VTH POWER SUPPLIES DVCC, Operating Range DVCC, Quiescent Current AVCC, Operating Range AVCC, Quiescent Current OPERATING TEMPERATURE Ambient Temperature Range, TA 7 Ambient Temperature Range, TA7
1
Conditions AVCC - VOH, VOL - AGND VIDx = 5 V step VIDx = 10 V step
Min
Typ 0.9 0.06 15.7 16.2
Max 1.3 0.150 4 4
Unit V V ns ns ns ns mA V V V k A A Bits
100 28 VRH VRL VRH VRL To VRL 5.25 VRL 0 22 -44 111 12 AVCC - 4 VRL + 2.75 2.75
Binary Coding TA MIN to TA MAX CLK input duty cycle 40% to 60% DSW = HIGH DSW = LOW
110 85 0 0 3.5 3.5 2.5 3.0 3.5 4.0 3 0.05 333 0.05 -0.6 -1.3 -1.2 2 0.8 1.65 3 11 75 3.3 54 3.6 70 18 100 75 85
DSW = HIGH DSW = HIGH DSW = LOW DSW = LOW
MHz MHz ns ns ns ns ns ns ns ns pF A A A A A A V V V V mA V mA C C
Still air, TSW = LOW 200 lfm airflow, TSW = LOW
0 0
VDE = differential error voltage, VCME = common-mode error voltage, VDE = VDE matching between outputs, V = maximum deviation between outputs, and full-scale output voltage = VFS = 2 x (VRH - VRL). See the Accuracy section. Guaranteed monotonic by characterization to four sigma limits. 3 Measured on two outputs differentially as CLK and DBx(0:11) are driven and XFR is held LOW. 4 Measured on two outputs differentially as the others are transitioning by 5 V. Measured for both states of INV. 5 Measured from 50% of rising CLK edge to 50% of output change. Measurement is made for both states of INV. 6 Measured from 50% of INV transition to 50% of output change. 7 Operation at elevated ambient temperature requires a thermally optimized PCB and additional thermal management, such as airflow across the surface of the AD8387.
2
Rev. 0 | Page 4 of 16
AD8387 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltages AVCCx - AGNDx DVCC - DGND Input Voltages Maximum Digital Input Voltage Minimum Digital Input Voltage Maximum Analog Input Voltage Minimum Analog Input Voltage Internal Power Dissipation1 TQFP E-Pad @ TA = 25C Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 10 sec)
1
Rating 18 V 4.5 V DVCC + 0.5 V DGND - 0.5 V AVCC + 0.5 V AGND - 0.5 V 4.38 W 0C to 85C -65C to +125C 300C
When TSW is HIGH, the output current limiter, as well as the thermal switch, is enabled. The thermal switch debiases the output amplifier when the junction temperature reaches the internally set trip point. In the event of an extended shortcircuit between a video output and a power supply rail, the output amplifier current continues to switch between 0 and 100 mA typical with a period determined by the thermal time constant and the hysteresis of the thermal trip point. The thermal switch, when enabled, provides long-term protection from accidental shorts during the assembly process by limiting the average junction temperature to a safe level.
MAXIMUM POWER DISSIPATION
The maximum power that the AD8387 can safely dissipate is limited by its junction temperature. The maximum safe junction temperature for plastic encapsulated devices, as determined by the glass transition temperature of the plastic, is approximately 150C. Exceeding this limit temporarily can cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 150C for an extended period can result in device failure.
80-lead TQFP E-Pad: JA = 28.5C/W (still air) [JEDEC Standard, 4-layer PCB in still air] JC = 12.2C/W JB = 14.6C/W JB = 12.0C/W JT = 0.3C/W.
Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings for extended periods may reduce device reliability.
OPERATING TEMPERATURE RANGE
To ensure operation within the specified operating temperature range, it is necessary to limit the maximum power dissipation as follows.
3.0 500LFM 200LFM 2.5
EXPOSED PADDLE
To ensure optimized thermal performance, the exposed paddle must be thermally connected to an external plane, such as AVCC or GND, as described in the Applications section.
MAXIMUM POWER DISSIPATION (W)
STILL AIR 2.0
OVERLOAD PROTECTION
The AD8387 overload protection circuit consists of an output current limiter and a thermal switch. When TSW is LOW, the thermal switch is disabled and the output current limiter is enabled. The maximum current at any one output is internally limited to 100 mA average. In the event of a momentary short-circuit between a video output and a power supply rail (VCC or AGND), the output current limit is sufficiently low to provide temporary protection.
1.5 QUIESCENT
05653-002
THERMAL SWITCH ENABLED DISABLED
1.0 50 75
55 80
60 65 70 75 80 85 85 90 95 100 105 110 AMBIENT TEMPERATURE (C)
90 115
95 120
100 125
Figure 3. Maximum Power Dissipation vs. Temperature, AD8387 on a 4-Layer JEDEC PCB with Thermally Optimized Landing Pattern as Described in the Applications Section
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 5 of 16
AD8387 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVCC0, 1
60 PIN 1 59 58 57 56 55
AGNDD
AGNDD
AVCCD
AVCCD
DGND2
AGND0
DVCC2
DBA4
DBA3
DBA2
BBA1
DBA0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DBA5 1 DBA6 DBA7 DBA8 DBA9 DBA10 DBA11 XFR DVCC1
2 3 4 5 6 7 8 9
VID0
VRH
VRH
VRL
NC
NC
NC
VID1 AGND1, 2 VID2 AVCC2, 3 VID3 AGND3, 4 VID4 AVCC4, 5 VID5 AGND5, 6 VID6 AVCC6, 7 VID7 AGND7, 8 VID8 AVCC8, 9 VID9 AGND9, 10 VID10 AVCC10, 11
AD8387
TOP VIEW (Not to Scale)
54 53 52 51 50 49 48 47 46 45 44 43 42 41
DGND1 10 CLK 11 DSW 12 R/L 13 DBB11 14 DBB10 15 DBB9 16 DBB8 17 DBB7 18 DBB6 19 DBB5 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AGND11
DGND3
DVCC3
AGNDB
AGNDB
AVCCB
AVCCB
VID11
INV
GSW
TSW
BYP
ISW
DBB4
DBB3
DBB2
DBB1
DBB0
TSTA
NC
NC = NO CONNECT
Figure 4. 80-Lead TQFP E-Pad Pin Configuration
Rev. 0 | Page 6 of 16
05653-004
AD8387
Table 3. 80-Lead TQFP E-Pad Pin Configurations
Pin No. 1 to 7, 76 to 80; 14 to 25 8 9, 26, 75 10, 27, 74 11 12 13 28 29 30 31 32, 33, 39, 43, 47, 51, 55, 59, 63, 69, 70 34, 35, 41, 45, 49, 53, 57, 61, 67, 68 36 37 38, 71 to 73 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62 64 65, 66 Mnemonic DBA(0:11) DBB(0:11) XFR DVCCx DGNDx CLK DSW R/L ISW INV GSW TSW AGNDx Function Data Input Data Input Transfer/Start Sequence Digital Power Supplies Digital Ground Clock Data Mode Switch Right/Left Select Invert Mode Switch Invert Output Mode Switch Thermal Switch Analog Ground Description 12-Bit Data Input for Even Channels. VID(0, 2, 4, 6, 8, 10), MSB = DBA11. 12-Bit Data Input for Odd Channels. VID(1, 3, 5, 7, 9, 11), MSB = DBB11. Simultaneously initiates a new data loading sequence and transfers data loaded previously, to the outputs. Digital Power Supplies. These pins are normally connected to the digital ground plane. Clock Input. Selects Single Buss or Dual Buss Operating Modes. Selects Left Direction or Right Direction Operating Mode. Enables and Disables Column Inversion. Changes the Polarity of the Analog Output Signals. Enables and Disables Grounded Mode. Enables and Disables Long-Term Output Protection. Analog Supply Returns.
AVCCx
Analog Power Supplies
Analog Power Supplies.
BYP TSTA NC VID0 to VID11
Bypass Test Pin NC Analog Outputs
A 0.1 F capacitor connected between BYP and AGND ensures optimum settling time. Connect This Pin to AGND. No Connect. No internal connection. These pins are connected directly to the analog inputs of the LCD panel.
VRL VRH
Video Center Reference Full-Scale Reference
This Voltage Sets the Video Center Voltage. The video outputs are above this reference while INV = HIGH and below this reference while INV = LOW. Twice the voltage applied between VRH and VRL sets the full-scale video output voltage.
Rev. 0 | Page 7 of 16
AD8387 TYPICAL PERFORMANCE CHARACTERISTICS
5.0 4.5 4.0
5.0 4.5
VDE CHANNEL MATCHING (mV)
4.0 3.5 3.0 CODE 0 2.5 2.0 1.5 1.0 0.5 0 0 10 20 30 40 50 60 70 80 AMBIENT TEMPERATURE (C) CODE 4095
05653-019
CHANNEL MATCHING (mV)
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 512 1024 1536 2048 2560 3072 3584 INPUT CODE VN
05653-016
VP
CODE 2048
VDE
4096
Figure 5. Channel Matching vs. Code @ TA = 25C
Figure 8. Channel Matching vs. TA @ Codes 0, 2048, 4095
3.5
5 4 3 2
2.5 1.5
VDE (mV)
1 0 -1 -2 -3 -4 -5 0 512 1024 1536 2048 2560 3072 3584 INPUT CODE
05653-018
VCME (mV)
0.5
-0.5
-1.5 -2.5 -3.5 0 512 1024 1536 2048 2560 3072 3584 INPUT CODE
4096
4096
Figure 6. VDE vs. Code
1.0 0.8 0.6 0.4
1.0 0.8 0.6 0.4
Figure 9. VCME vs. Code
DNL (LSB)
DNL (LSB)
0.2 0 -0.2 -0.4 -0.6
05653-017
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 INPUT CODE
05653-020
-0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 INPUT CODE
4096
4096
Figure 7. DNL vs. Code @ TA = 25C, INV = H
Figure 10. DNL vs. Code @ TA = 25C, INV = L
Rev. 0 | Page 8 of 16
05653-021
AD8387 TIMING DIAGRAMS
SINGLE DATA BUS CONFIGURATION, DSW = LOW
12 D(0:11)
DBA(0:11) DBB(0:11) VID0 VID1 VID2
12-CHANNEL LCD CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 CHANNEL 8 CHANNEL 9 CHANNEL 11
05653-005
PIXEL CLK
/2
CLK XFR R/L INV
CLK XFR R/L INV REFERENCES VRH VRL DSW ISW VRH VRL
AD8387
VID3 VID4 VID5 VID6 VID7 VID8 VID9 VID10 VID11
IMAGE PROCESSOR
CHANNEL 10
Figure 11. AD8387 in Single Data Bus System
LEFT PIXEL CLK PIXEL CLK
RIGHT
D(0:11) -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CLK XFR
D(0:11) -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CLK XFR
INPUTS
R/L
INPUTS
R/L
VID0 VID1 VID2 VID3 VID4
OUTPUTS
-12 -11 -10 -9 -8 -7
0 1 2 3 4 5
12 13 14 15 16
OUTPUTS
VID0 VID1 VID2 VID3 VID4 VID5
-1 -2 -3 -4 -5 -6
11 10 9 8 7 6
23 22 21 20 19 18
VID5
17
VID6 VID7 VID8 VID9 VID10 VID11
-6 -5 -4 -3 -2 -1
6 7 8 9 10 11
18 19 20 21 22 23
VID6 VID7 VID8 VID9 VID10 VID11
-7 -8 -9 -10 -11 -12
5 4 3 2 1 0
17 16 15 14 13 12
05653-006
Figure 12. AD8387 in Single Data Bus Configuration Scanning Left-to-Right and Right-to-Left
Rev. 0 | Page 9 of 16
AD8387
DUAL DATA BUS CONFIGURATION, DSW = HIGH
12 DA(0:11) 12 DB(0:11) PIXEL CLK /2 CLK XFR R/L INV IMAGE PROCESSOR REFERENCES VRH VRL DVCC DSW ISW VRH VRL DBB(0:11) CLK XFR R/L INV VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID8 VID9 VID10 VID11 CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 CHANNEL 6 CHANNEL 7 CHANNEL 8 CHANNEL 9 CHANNEL 10 CHANNEL 11
05653-007
DBA(0:11)
12-CHANNEL LCD
AD8387
Figure 13. AD8387 in Dual Data Bus System
LEFT PIXEL CLK PIXEL CLK
RIGHT
DBA(0:11) DBB(0:11)
INPUTS
-2 -1
0 1
2 3
4 5
6 7
8 9
10 11
12 13
14 15
16 17
18 19
20 21
22 23
24 25
INPUTS
DBA(0:11) DBB(0:11) CLK XFR
-1 -2
1 0
3 2
5 4
7 6
9 8
11 10
13 12
15 14
17 16
19 18
21 20
23 22
25 24
CLK XFR
R/L
R/L
VID0 VID1 VID2 VID3 VID4
OUTPUTS
-12 -11 -10 -9 -8 -7
0 1 2 3 4 5
12 13 14 15 16
OUTPUTS
VID0 VID1 VID2 VID3 VID4 VID5
-1 -2 -3 -4 -5 -6
11 10 9 8 7 6
23 22 21 20 19 18
VID5
17
VID6 VID7 VID8 VID9 VID10 VID11
-6 -5 -4 -3 -2 -1
6 7 8 9 10 11
18 19 20 21 22 23
VID6 VID7 VID8 VID9 VID10 VID11
-7 -8 -9 -10 -11 -12
5 4 3 2 1 0
17 16 15 14 13 12
05653-008
Figure 14. AD8387 in Dual Data Bus Configuration Scanning Left-to-Right and Right-to-Left
Rev. 0 | Page 10 of 16
AD8387
t6
CLK
t5 t1 t2 t1 t2
VTH
DB(0:11)
VTH
05653-009
XFR
t3
t4
VTH
Figure 15. Input Timing (DSW = LOW)
CLK DB(0:11) XFR INV VRL + VFS VID(0:11) 50% VRL VRL -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
t7
t8
PIXELS 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
05653-010
t7
PIXELS -12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, -1
VRL-VFS
Figure 16. Output Timing (DSW = LOW)
Table 4.
Parameter Data Setup Time: t1 XFR Setup Time: t3 Data Hold Time: t2 XFR Hold Time: t4 CLK High Time: t5 CLK Low Time: t6 CLK High Time: t7 CLK Low Time: t8 Data Switching Delay: t7 Data Switching Delay Skew: t7 Invert Switching Delay: t8 Invert Switching Delay Skew: t8 Conditions Min 0 0 3.5 3.5 2.5 3.0 3.5 4.0 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns
DSW = HIGH DSW = HIGH DSW = LOW DSW = LOW VIDx = 5 V step
15.7 4 16.2 4
Rev. 0 | Page 11 of 16
AD8387 FUNCTIONAL DESCRIPTION
The AD8387 is a system building block designed to directly drive the columns of LCD microdisplays of the type popularized for use in projection systems. It has 12 channels of precision, 12-bit DACs loaded from a dual, high speed, 12-bit wide input. Precision current feedback amplifiers, providing well damped pulse response and fast voltage settling into large capacitive loads, buffer the 12 outputs. Laser trimming at the wafer level ensures low absolute output errors and tight channel-to-channel matching. Tight part-to-part matching in high resolution systems is guaranteed by the use of external voltage references.
Right/Left Control--Input Data Loading
To facilitate image mirroring, the direction of the loading sequence is set by the R/L control. A new loading sequence begins at Channel 0 and proceeds to Channel 11 when the R/L control is held LOW. It begins at Channel 11 and proceeds to Channel 0 when the R/L control is held HIGH. TSW Control--Thermal Switch Control When this input is HIGH, the thermal switch is enabled. When LOW or left unconnected, the thermal switch is disabled. An internal, 10 k pull-down resistor disables the thermal switch when this pin is left unconnected.
REFERENCE AND CONTROL INPUT DESCRIPTION
Data Transfer/Start Sequence Control--Input Data Loading, Data Transfer
A valid XFR is initiated when it is held HIGH during a rising CLK edge. Data is transferred to the outputs and a new loading sequence is initiated on the next rising CLK edge, immediately following a valid XFR. During a loading sequence, 12-bit words are loaded sequentially into 12 internal channels. When the AD8387 is configured for single data bus (DSW = LOW), data is loaded on both the rising and falling edges of CLK. When configured for dual data bus (DSW = HIGH), data is loaded on the rising edges of CLK only.
GSW Control--Output Mode Switch
When this input is HIGH, the video outputs operate normally. When LOW or left open, the video outputs are forced to AGND. This function operates when AVCC power is off but requires DVCC power to be on.
INV Control and ISW Control--Analog Output Inversion
When ISW = LOW, the analog outputs' transfer function is below VRL, while INV is held LOW, and is above VRL, while INV is held HIGH. With ISW = HIGH, the analog outputs' transfer function is above VRL for VID(0, 2, 4, 6, 8, 10) and is below VRL for VID(1, 3, 5, 7, 9, 11), while INV is held HIGH. Conversely, the analog outputs' transfer function is below VRL for VID(0, 2, 4, 6, 8, 10) and is above VRL for VID(1, 3, 5, 7, 9, 11), while INV is held LOW. VRH, VRL Inputs--Full-Scale Video Reference Inputs Two times the difference between VRH and VRL (analog input voltages) sets the full-scale output voltage. VFS = 2 x (VRH - VRL)
DSW Control--Data Mode Switch
When this input is HIGH, the AD8387 is in dual data bus mode. Data is loaded from both DBA(0:11) and DBB(0:11) on the rising CLK edge simultaneously. R/L does not change the active CLK edge in dual data bus mode. When LOW, the AD8387 is in single data bus mode. Data is loaded on the rising CLK edge from DBA(0:11) and on the falling CLK edge from DBB(0:11) when R/L is LOW. With R/L HIGH, data is loaded on the falling CLK edge from DBA(0:11) and on the rising CLK edge from DBB(0:11).
Rev. 0 | Page 12 of 16
AD8387 THEORY OF OPERATION
TRANSFER FUNCTION AND ANALOG OUTPUT VOLTAGE
The DecDriver has two regions of operation where the video output voltages are either above or below the reference voltage VRL. The transfer function defines the video output voltage as the function of the digital input code as: VOUTN(n) = VIDx(n) = VRL + VFS x (1 - n/4095), for INV = HIGH VOUTP(n) = VIDx(n) = VRL - VFS x (1 - n/4095), for INV = LOW where n is the input code. VFS = 2 x (VRH - VRL) A number of internal limits define the usable range of the video output voltages, VIDx, as shown in Figure 17.
VIDx - VOLTS AVCC (VRL + VFS) 1.3V
ACCURACY
To best correlate transfer function errors to image artifacts, the overall accuracy of the DecDriver is defined by three parameters, VDE , VCME, and VDE. VDE, the differential error voltage, measures the difference between the rms value of a channel and the ideal rms value of that channel. The defining expression is
VOUTN(n) - VOUTP(n) - 1 - n x VFS VDE(n) = 2 4095 VCME, the common-mode error voltage, measures 1/2 the dc bias of a channel. The defining expression is VCME(n) = 1 VOUTN (n) + VOUTP(n) - VRL 2 2
VDE measures the maximum VDE mismatch between channels. The defining equation is VDE = max{VDE(n)(0 - 11)} - min{VDE(n)(0 - 11)}
VOUTN
0 VFS 5.25V
VRL
11V AVCC 18V 0 VFS 5.25V
V measures the maximum mismatch between channels. The defining expression is V(n) = max{VN(n), VP(n)} where: VN(n) = max{VOUTN(n)(0 - 11)} - min{VOUTN(n)(0 - 11)}
VOUTP
5.25V VRL (AVCC - 4)
(VRL - VFS) AGND 0 INPUT CODE VIDx vs. INPUT CODE 4095
1.3V
05653-011
INTERNAL LIMITS AND USABLE VOLTAGE RANGES
VP(n) = max{VOUTP(n)(0 - 11)} - min{VOUTP(n)(0 - 11)}
Figure 17. AD8387 Transfer Function and Usable Voltage Ranges
Rev. 0 | Page 13 of 16
AD8387 APPLICATIONS
OPTIMIZED RELIABILITY WITH THE THERMAL SWITCH
While internal current limiters provide short-term protection against temporary shorts at the outputs, the thermal switch provides protection against persistent shorts lasting for several seconds. To optimize reliability with the use of the thermal switch, the following sequence of operations is recommended.
POWER-OFF SEQUENCE
1. 2. 3. 4. 5. Turn off input signals Turn off VRL Turn off VRH Turn off AVCC Turn off DVCC
INITIAL POWER-UP AFTER ASSEMBLY OR REPAIR
Grounded output mode is disabled, and thermal switch is enabled. Ensure that the GSW pin is HIGH and that the TSW pin is HIGH upon initial power-up and that they remain unchanged throughout this procedure. The initial power-up sequence follows: 1. Execute the initial power-up. 2. Identify any shorts at outputs. Power down, repair shorts, and repeat the initial power-up sequence until proper system functionality is verified. 3. Disable the thermal switch.
GROUNDED OUTPUT MODE DURING POWER-OFF
Certain applications require that video outputs be held near AGND during power-down. The following power-off sequence ensures that the outputs are near ground during power-off and that the Absolute Maximum Ratings are not violated. 1. 2. 3. 4. 5. 6. Enable grounded output mode: GSW = LOW Turn off input signals Turn off VRL Turn off VRH Turn off AVCC Turn off DVCC
POWER-UP DURING NORMAL OPERATION
Grounded output mode is disabled, and thermal switch is disabled. If TSW = LOW and GSW = HIGH, all outputs go into normal operating mode with the thermal switch disabled.
PCB DESIGN FOR OPTIMIZED THERMAL PERFORMANCE
Although the maximum safe operating junction temperature is higher, the AD8387 is 100% tested at a junction temperature of 125C. Consequently, the maximum guaranteed operating junction temperature is 125C. To limit the maximum junction temperature at or below the guaranteed maximum, the package in conjunction with the PCB must effectively conduct heat away from the junction. The AD8387 package is designed to provide enhanced thermal characteristics through the exposed die paddle on the bottom surface of the package. To take full advantage of this feature, the exposed paddle must be in direct thermal contact with the PCB, which then serves as a heat sink. A thermally effective PCB must incorporate two thermal pads and a thermal via structure. The thermal pad on the top surface of the PCB provides a solderable contact surface on the top surface of the PCB. The thermal pad on the bottom PCB layer provides a surface in direct contact with the ambient. The thermal via structure provides a thermal path to the inner and bottom layers of the PCB to remove heat.
POWER SUPPLY SEQUENCING
As indicated under the Absolute Maximum Ratings, the voltage at any input pin cannot exceed its supply voltage by more than 0.5 V. Power-on and power-off sequencing can be required to comply with the absolute maximum ratings. Failure to comply with the Absolute Maximum Ratings can result in functional failure or damage to the internal ESD diodes. Damaged ESD diodes can cause temporary parametric failures, which can result in image artifacts. Damaged ESD diodes cannot provide full ESD protection, reducing reliability.
POWER-ON SEQUENCE
1. 2. 3. 4. 5. 6. Turn on AVCC Turn on VRH Turn on VRL Turn on DVCC Disable thermal switch: TSW = LOW Turn on input signals
Rev. 0 | Page 14 of 16
AD8387
THERMAL PAD DESIGN
To minimize thermal performance degradation of production PCBs, the contact area between the thermal pad and the PCB should be maximized. Therefore, the size of the thermal pad on the top PCB layer should match the exposed paddle. The second thermal pad of the same size should be placed on the bottom side of the PCB. At least one thermal pad should be in direct thermal contact with an external plane, such as AVCC or GND.
16mm
6.5mm
6.5mm
THERMAL VIA STRUCTURE DESIGN
Effective heat transfer from the top to the inner and bottom layers of the PCB requires thermal vias incorporated into the thermal pad design. Thermal performance increases logarithmically with the number of vias. Near optimum thermal performance of production PCBs is attained only when tightly spaced thermal vias are placed on the full extent of the thermal pad.
05653-012
16mm
Figure 18. Land Pattern--Top Layer
6.5mm
6.5mm
Thermal Pad and Thermal via Connections
The thermal pad on the solder side is connected to a plane. The use of thermal spokes is not recommended when connecting the thermal pads or via structure to the plane.
Solder Masking
Solder masking of the via holes on the top layer of the PCB plugs the via holes, inhibiting solder flow into the holes. To minimize the formation of solder voids due to solder flowing into the via holes (solder wicking), via diameter should be made small, and an optional solder mask can be used. To optimize the thermal pad coverage when using the solder mask, its diameter should be no more than 0.1 mm larger than the via hole diameter. Pads are set by customer's PCB design rules.
Thermal via Holes--Circular mask, centered on the via holes. Diameter of the mask should be 0.1 mm larger than the via hole diameter.
Figure 19. Land Pattern--Bottom Layer
Figure 20. Solder Mask--Top Layer
Solder Mask--Bottom Layer
This is set by customer's PCB design rules.
AD8387 PCB DESIGN RECOMMENDATIONS
Table 5. Land Pattern Dimensions
Pad Size 0.6 mm x 0.25 mm Pad Pitch 0.5 mm Thermal Pad Size 6 mm x 6 mm Thermal Via Structure 0.25 mm - 0.35 mm holes 0.5 mm - 1.0 mm grid
Rev. 0 | Page 15 of 16
05653-013
05653-014
AD8387 OUTLINE DIMENSIONS
14.20 14.00 SQ 13.80 0.75 0.60 0.45 1.20 MAX
80 1 PIN 1
12.20 12.00 SQ 11.80
61 60 60 61 80 1
TOP VIEW
(PINS DOWN)
EXPOSED PAD
6.00 BSC SQ
1.05 1.00 0.95
0 MIN
BOTTOM VIEW
(PINS UP) 20 21 40 41 41 40 20 21
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.08 MAX COPLANARITY
VIEW A
0.50 BSC LEAD PITCH
0.27 0.22 0.17
VIEW A
ROTATED 90 CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD
Figure 21. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] (SV-80-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8387JSVZ 1 AD8387-EB
1
Temperature Range 0C to 85C
Package Description 80-Lead TQFP Evaluation Board
Package Option SV-80-1
Z = Pb-free part.
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05653-0-10/05(0)
Rev. 0 | Page 16 of 16

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